View LTC4231HUD-1PBF_8541676.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc 4231 1 4321fa for more information www.linear.com/ltc4231 typical application features description micropower hot swap controller the lt c ? 4231 is a micropower hot swap? controller that allows safe circuit board insertion and removal from a live power supply. an internal high side switch driver controls the gate of an external n-channel mosfet. back-to-back mosfets can be used for reverse supply protection down to C40v. the ltc4231 provides a debounce delay and allows the gate to be ramped up at an adjustable rate. after start- up, the ltc4231's quiescent current drops to 4 a during normal operation with output active. uvl, uvh, ov and gndsw monitor overvoltage and undervoltage periodi - cally, keeping total quiescent current low. pulling shdn low shuts down the ltc4231 and quiescent current drops to 0.3a. during an overcurrent fault, the ltc4231 actively limits current while running an adjustable timer. the ltc4231-1 remains off after a current fault while the ltc4231-2 automatically reapplies power after a cool-down period. l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. battery hot swap with reverse protection applications n enables safe board insertion and removal from a power supply n 4a supply current n 0.3a shutdown current n wide operating voltage range: 2.7v to 36v n reverse supply protection to ?40v n adjustable analog current limit with circuit breaker n automatic retry or latchoff on current fault n overvoltage and undervoltage monitoring n controls single or back-to-back n-channel mosfets n 12-lead msop and 3mm 3mm qfn packages n battery powered equipment n solar powered systems n portable instruments n automotive battery protection n energy harvesting sense gate inuvl uvh ov gndsw source status shdn timer ltc4231 si7164dp smaj24ca 22.5m si5410du gnd 20k 220f v out 24v2a 1020k 1.65k 24v 4.22k 32.4k 180nf 4231 ta01a gate 20v/div in 20v/div source 20v/div i load 5a/div 10ms/div 4231 ta01b contact bounce power-up waveforms downloaded from: http:///
ltc 4231 2 4321fa for more information www.linear.com/ltc4231 absolute maximum ratings supply voltage in ............................................................ C40 v to 40 v input voltages sense , s ource ..................................... C40 v to 40 v in C sense ............................................... C40 v to 40 v shdn , u vl , uvh , ov , gndsw .............. C0.3 v to 40 v input currents shdn , u vl , uvh , ov , gndsw ( note 3) ............ C1 ma output voltages gate C s ource ( no te 4) ......................... C0.3 v to 13 v (notes 1, 2) order information lead free finish tape and reel part marking package description temperature range ltc4231cud-1#pbf ltc4231cud-1#trpbf lgmx 12-lead (3mm 3mm) plastic qfn 0c to 70c ltc4231cud-2#pbf ltc4231cud-2#trpbf lgsp 12-lead (3mm 3mm) plastic qfn 0c to 70c ltc4231iud-1#pbf ltc4231iud-1#trpbf lgmx 12-lead (3mm 3mm) plastic qfn C40c to 85c ltc4231iud-2#pbf ltc4231iud-2#trpbf lgsp 12-lead (3mm 3mm) plastic qfn C40c to 85c ltc4231hud-1#pbf ltc4231hud-1#trpbf lgmx 12-lead (3mm 3mm) plastic qfn C40c to 125c ltc4231hud-2#pbf ltc4231hud-2#trpbf lgsp 12-lead (3mm 3mm) plastic qfn C40c to 125c 12 11 10 4 5 6 top view 13 ud package 12-lead (3mm 3mm) plastic qfn 7 8 9 3 2 1 shdn uvl uvh sourcetimer status insense gate ov gndsw gnd t jmax = 150c, ja = 68c/w exposed pad (pin 13) pcb connection to gnd is op tional 12 3 4 5 6 sense in shdn uvl uvh ov 1211 10 9 8 7 gate source timer status gnd gndsw top view ms package 12-lead plastic msop t jmax = 150c, ja = 135c/w pin configuration gate C sense .......................................... C40 v to 20 v status ................................................. C0.3 v to 40 v timer ...................................................... C0.3 v to 4v operating ambient temperature range ltc 4 231 c ................................................ 0 c to 70 c ltc 4231 i .............................................. C40 c to 85 c ltc 4231 h .......................................... C40 c to 125 c storage temperature range .................. C65 c to 150 c lead temperature ( soldering , 10 sec ) msop package ................................................. 300 c downloaded from: http:///
ltc 4231 3 4321fa for more information www.linear.com/ltc4231 order information electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. in = 12v, unless otherwise noted. symbol parameter conditions min typ max units inv in input supply voltage range l 2.7 36 v v in(uvl) input supply undervoltage lockout in rising l 2 2.3 2.6 v ?v in(hyst) input supply undervoltage lockout hysteresis 200 mv i cc supply current (average) normal on, voltage or current fault start-up or overcurrent shutdown reverse input (note 5) i gate C0.1 a , c gate - source = 1 nf , ( c- grade, i- grade ) (h-grade) shdn low, gate pulled to gnd, (c-grade, i-grade) (h-grade) in, sense = C40v l l l l l l 4 4 300 0.3 0.3 C2.5 10 20 600 1 2 C5 a a a a a ma sense ?v sense(cb) circuit breaker threshold (v in C v sense ) l 47 50 53 mv ?v sense(acl) analog current limit during output short-circuit l 65 80 90 mv i sense sense input current shdn = high, sense = 12v l 0.3 1 a gate, source ?v gate external n-channel gate drive (v gate C v source ) v in < 7v, i gate = 0, C0.1a v in 7v, i gate = 0, C0.1a l l 4.5 10 6.2 11.4 10 18 v v ?v gate(h) ?v gate (v gate C v source ) threshold that deactivates the charge pump v in < 7v v in 7v l l 5.5 11 6.5 11.7 10 18 v v v gate(l) gate low threshold to enter shutdown or voltage fault l 0.4 1.2 1.8 v i gate(up) gate pull-up current gate on, gate = 1v l C7 C10 C13 a i gate(fast) gate fast pull-down current ?v sense = 0.5v, ?v gate = 5v l 70 130 ma i gate(slow) gate slow pull-down current shdn = 0v, ?v gate = 5v l 0.6 1 ma t d(on) turn-on debounce delay uvl = uvh = 2v, ov = 0v, shdn = step 0v to 5v l 20 40 60 ms t retry auto-retry delay ltc4231-2 l 0.27 0.5 0.73 s t phl(ilim) overcurrent to gate low propagation delay ?v sense = step 0mv to 300mv, c gate = 1nf, ?v gate crosses 1v l 0.5 1 s lead free finish tape and reel part marking package description temperature range ltc4231cms-1#pbf ltc4231cms-1#trpbf 42311 12-lead plastic msop 0c to 70c ltc4231cms-2#pbf ltc4231cms-2#trpbf 42312 12-lead plastic msop 0c to 70c ltc4231ims-1#pbf ltc4231ims-1#trpbf 42311 12-lead plastic msop C40c to 85c ltc4231ims-2#pbf ltc4231ims-2#trpbf 42312 12-lead plastic msop C40c to 85c ltc4231hms-1#pbf ltc4231hms-1#trpbf 42311 12-lead plastic msop C40c to 125c ltc4231hms-2#pbf ltc4231hms-2#trpbf 42312 12-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc 4231 4 4321fa for more information www.linear.com/ltc4231 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. in = 12v, unless otherwise noted. symbol parameter conditions min typ max units uvl, uvh, ov, gndsw, status and shdn v uv uvl, uvh threshold l 0.776 0.795 0.814 v v ov ov threshold ov rising l 0.776 0.795 0.814 v v ov(hyst) ov hysteresis l 3 15 30 mv i leak(0.9v) uvl, uvh and ov leakage current v = 0.9v ( c- grade, i- grade ) (h-grade) l l 0 0 10 100 na na i leak(12v) uvl, uvh, ov, gndsw, status and shdn leakage current v = 12v ( c- grade, i- grade ) (h-grade) l l 0 0 100 500 na na r on(gndsw) switch resistance l 80 200 v ol status output low voltage i = 2ma l 0.2 0.4 v v shdn shdn input threshold l 0.4 0.8 1.5 v t period sampling period l 5 10 15 ms t sample sampling width l 100 200 300 s timert cb circuit breaker delay c t = 100nf l 1.7 2.4 3.5 ms v timer(h) timer high threshold timer rising l 1.170 1.193 1.216 v v timer(l) timer low threshold timer falling l 0.07 0.1 0.13 v i timer(up) timer pull-up current timer = 0.5v, circuit breaker tripped l C35 C50 C65 a i timer(dn) timer pull-down current timer = 0.5v, circuit breaker recovery l 3 5 7 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless other wise specified. note 3: these pins can be tied to voltages below C0.3v through a resistance that limits the current below 1ma.note 4: an internal clamp limits gate to a minimum of 13v above source. driving this pin to voltages beyond this clamp may damage the device. note 5: for modes where gate is pulled to gnd, i cc = i in + i sense . else i cc = i in + i sense + i source . downloaded from: http:///
ltc 4231 5 4321fa for more information www.linear.com/ltc4231 average supply current vs in average supply current (normal on) vs gate leakage average supply current vs temperature typical performance characteristics v in (v) 0 0 i cc (a) 3 41 2 5 10 20 30 4231 g01 40 normal oni gate = C 0.1a shutdown i gate (a) C0.01 1 i cc (a) 10 100 1000 C0.1 C1 C10 4231 g02 C100 v in = 12v temperature (c) C50 0.1 i cc (a) 1 10 100 C25 0 25 50 75 125 100 4231 g03 150 v in = 12v normal oni gate = C1a normal oni gate = C0.1a normal oni gate = 0 shutdown supply current (reverse input) vs in ?v gate (average) vs in ?v gate (average) vs gate leakage v in (v) 0 0 i cc (ma) C1 C2 C3 C10 C30 C20 4231 g04 C40 v in (v) i gate = C0.1a 0 4 ?v gate (v) 6 8 10 12 14 10 30 20 4231 g05 40 i gate (a) v in = 12v v in = 2.7v 0 0 ?v gate (v) 6 82 4 10 12 14 16 C6 C10 C8 C2 C4 4231 g06 C12 downloaded from: http:///
ltc 4231 6 4321fa for more information www.linear.com/ltc4231 typical performance characteristics gate pull-up current vs v gate overcurrent to gate low propagation delay uvl, uvh, ov thresholds vs temperature gndsw switch resistance vs in status output low voltage vs current status output low voltage vs temperature v gate (v) v in = 12v 0 0 i gate(up) (a) C5 C10 C15 C20 15 20 5 10 4231 g07 25 v in C v sense (mv) c gate = 1nf c timer = 82nf 50 0.1 overcurrent to gate low propagation delay (s) 1 10 100 1000 200 350 100 150 300 250 4231 g08 400 temperature (c) v in = 12v uvl high to lowuvh low to high ov low to high ov high to low C50 0.770 threshold (v) 0.775 0.780 0.785 0.790 0.795 0.800 100 75 125 25 50 C25 0 4231 g09 150 v in (v) 0 70 r on(gndsw) () 80 90 100 110 20 30 10 4231 g10 40 i status (ma) v in = 12v 0 0 v status (mv) 100 200 300 400 500 600 4 3 2 1 4231 g11 5 temperature (c) v in = 12v i status = 2ma C50 0 v status (mv) 100 200 300 400 100 75 125 25 50 C25 0 4231 g12 150 downloaded from: http:///
ltc 4231 7 4321fa for more information www.linear.com/ltc4231 pin functions gate: gate drive for external n-channel mosfet. after all start-up conditions are satisfied, a 10 a pull-up cur- rent from the internal charge pump charges up ? v gate to the high threshold voltage ? v gate(h) and then turns off. the charge pump turns on again when ? v gate decays by more than 0.7 v or every 15 ms, whichever comes first, and recharges ? v gate to ? v gate(h) . during gate turn- off, a 1 ma pull-down current discharges gate to gnd. during severe short circuits, a 130 ma pull-down current is activated to discharge gate to source. gnd: device ground. gndsw: switched gnd. connect this pin to an external resistive network to monitor in for overvoltage or under - voltage ( ov/uv). to reduce the power dissipated by this resistive divider, the ltc4231 periodically samples in by connecting gndsw to gnd once every 10 ms. tie this pin to gnd if unused.in: supply voltage and current sense input. this pin has a nominal undervoltage lockout threshold of 2.3v. shdn : shutdown control input. a logic high at shdn enables the ltc4231. gate ramps up after a debounce delay of 40 ms. a logic low at shdn activates a 1 ma pull- down current at gate, discharging it to gnd. once gate < 1.2 v, the ltc4231 enters a low current shutdown. connect to in if unused. when connected to in, if in goes below ground, use a resistor to limit the current to 1 ma. ov: overvoltage comparator input. connect this pin to an external resistive network to monitor in for ov. this pin connects internally to an overvoltage comparator with a 0.795v threshold. to reduce the power dissipated by this resistive divider, the ltc4231 periodically samples in by connecting gndsw to gnd once every 10 ms. once an ov is detected at in, gate and status pull low. tie this pin to gnd if unused. sense: current sense input. connect to the output of the current sense resistor. the circuit breaker comparator and the analog current limit amplifier monitor the voltage across the current sense resistor. during an overcurrent fault when ? v sense exceeds 50 mv, the circuit breaker comparator trips and triggers timer to ramp up. for more severe overcurrent faults, the analog current limit amplifier controls the gate of the external mosfet to keep ?v sense at 80 mv. to disable the circuit breaker comparator and analog current limit amplifier, connect this pin to in. source : n- channel mosfet source connection. connect this pin to the source of the external mosfet. status: status output. open-drain output that goes high impedance when ? v gate first exceeds ? v gate (h) . the state of the pin is latched and resets ( pulls low) when shdn goes low, an uvlo occurs, an ov/uv is detected at in or an overcurrent fault sets the internal current fault latch. this pin may be left open if unused. timer: timer input. connect a capacitor between this pin and gnd to set a 24 ms/f duration for overcurrent before the internal current fault latch trips and turns off the mosfet. for the ltc4231-1 latchoff option, the mosfet remains off until the current fault latch is cleared by pulling shdn low or by cycling power. for the ltc4231-2 auto- retry option, the current fault latch is cleared automatically and the gate is ramped up after a 500ms delay. uvh, uvl : undervoltage comparator input. connect these pins to an external resistive network to monitor in for uv. these pins connect internally to an undervoltage compara - tor with a 0.795 v threshold. the comparator monitors uvh when gate is low and uvl when gate is high to implement separate undervoltage turn-on and undervolt- age turn -off thresholds. to reduce the power dissipated by this resistive divider, the ltc4231 periodically samples in by connecting gndsw to gnd once every 10 ms. once an uv is detected at these pins, gate and status pull low. tie both pins to in if unused. when connected to in, for applications where in goes below ground, use a resistor to limit the current to 1ma. exposed pad ( qfn package): the exposed pad may be left open or connected to device ground. downloaded from: http:///
ltc 4231 8 4321fa for more information www.linear.com/ltc4231 functional diagram 4231 fd in sense voltage regulator + C +C +C C+ reverse voltage comparator C+ reverse voltage comparator ?v gate low comparator ?v gate(h) analog currentlimit amplifier + C + C charge pumprefresh timer 80mv +C circuit breaker comparator timer high comparator timer low comparator + C 50mv +C + C 1.2v 15v 0.795v 1ma charge pump f = 2mhz gate low comparator +C 0.795v +C uv comparator ov/uv block ov comparator 10a logic internal v cc internal v cc 1.193v 0.1v uvl source gate uvh ov gndsw status ov/uv strobe timer shdn gnd 5a 50a timer downloaded from: http:///
ltc 4231 9 4321fa for more information www.linear.com/ltc4231 operation the ltc4231 is a micropower hot swap controller that controls an external n-channel mosfet to turn on and off a supply voltage in a controlled manner. this allows a circuit to be safely inserted and removed from a powered connector without glitches or connector damage from uncontrolled inrush current. when the ltc4231 is first powered up, the gate of the mosfet is held at gnd to keep it off. pulling shdn high and in above undervoltage lockout ( uvlo) starts an internal clock that monitors the resistive divider at in once every 10ms by connecting gndsw to gnd. a 40 ms debounce cycle is also started. average i cc during this debounce mode is 4a. after the 40 ms debounce cycle, the ltc4231 goes into start-up mode to ramp up gate. in this mode, all circuits blocks except the overvoltage or undervoltage ( ov/uv) block are activated and i cc = 300 a. the internal charge pump supplies a 10 a pull-up current to gate. once ?v gate exceeds ? v gate(h) , status goes high impedance. this indicates that gate is high and the power path is on. average i cc drops to 4 a during this normal on mode as some circuit blocks are shut down and the internal charge pump periodically turns on to recharge gate as needed. the periodic monitoring of the in resistive divider continues as long as shdn is high and in 2.3v. if an ov/uv violation is detected during the in monitor - ing time , the part goes into voltage fault mode ( average i cc = 4 a) where gate and status is pulled to gnd. the debounce cycle restarts when no ov/uv violation is detected during a subsequent in monitoring window. the ltc4231 has a circuit breaker comparator that moni - tors the voltage across the current sense resistor. this comparator trips when ? v sense exceeds 50 mv, bringing the ltc4231 into overcurrent mode. in this mode, all circuits blocks except the ov/uv block are activated and i cc = 300 a. if ? v sense > 80 mv, the analog current limit amplifier limits ? v sense to 80 mv by servoing ? v gate in an active control loop. the timer capacitor is ramped up with a 50 a pull-up when ? v sense > 50 mv. when timer > 1.193 v, the current fault latch is set, causing gate and status to pull low. the part goes into current fault mode. in current fault mode, the latchoff ( ltc4231-1) version keeps timer and gate low. the auto-retry ( ltc4231-2) version waits 500 ms before gate is ramped up again. for both versions, the part can be reset by cycling shdn low then high or by cycling in to gnd and back. after the reset, the ltc4231 goes through a debounce cycle before re-starting gate. shdn acts as a shutdown switch for the supply path. when it goes high, the ltc4231 ramps gate up after a debounce cycle to turn on the external mosfet. when it goes low, gate is pulled to gnd to turn off the external mosfet. the ltc4231 then goes into shutdown mode where i cc drops to 0.3a. in, sense, gate and source are protected against reverse inputs of up to C40 v. tw o reverse voltage comparators detect negative input potentials at sense or gate and quickly connect gate to sense. when used with back- to-back mosfets as shown in figure 5, this feature will isolate the load from a negative input. downloaded from: http:///
ltc 4231 10 4321fa for more information www.linear.com/ltc4231 the micropower capability of the ltc4231 makes it ideal for hot swap applications in battery powered systems where current load is light or intermittent and power draw is a concern. it can implement battery short circuit protection, reverse battery protection, battery voltage monitoring, power path control, hot-plug and inrush current control in off-grid, autonomous systems. turn-on sequence when in is less than the uvlo level of 2.3 v or shdn is low, gate is pulled to gnd and status pulls low. when in 2.3 v and shdn goes high, an internal clock starts timing a 40 ms debounce cycle. the clock also times a 200s strobe of the resistive divider at in every 10 ms to make sure in is not in ov/uv. average i cc during this debounce mode is 4a.any ov / uv detected will stop and reset the debounce timing cycle. during this voltage fault mode, average i cc is 4 a. the debounce cycle only restarts when a subsequent in strobe indicates that the input power is within the accept - able range, in 2.3v and shdn is high. when the debounce cycle of 40 ms successfully completes , the ltc4231 turns on its charge pump, analog current limit amplifier and timer control circuit blocks as it goes applications information into start-up mode ( i cc = 300 a). the external mosfet is turned on by charging up the gate with a 10 a charge pump generated current source. at start-up, the mosfet current is typically dominated by the current charging the load capacitor c l . if ? v sense > 80mv, the analog current limit amplifier controls the gate of the mosfet in a closed loop. this keeps the start-up inrush current at 80mv/r sense . when ?v sense > 50mv, the timer capacitor charges up with an internal 50 a pull-up current. figure 2. inrush control by analog current limit sense gate inuvl uvh ov gndsw source status shdn timer ltc4231 m1 si7120adn r sense 22.5m gnd r stat 20k r52m c11nf r5 10? c g 20nf v out 24v2a gnd r11020k z1smaj24a c in 100f r21.65k 24v battery cell(s) uv rising = 23v uv falling = 22v ov rising = 26v r34.22k r432.4k c t 39nf i load 4231 f01 r g 1k r7 10m + + c l 1000f figure 1. channel controller with connector enable gate 20v/div out 20v/div timer 0.5v/div i load 2a/div 1ms/div start-up normal on debounce 4231 f02 downloaded from: http:///
ltc 4231 11 4321fa for more information www.linear.com/ltc4231 applications information in most applications, keeping the inrush current at ana- log current limit is an acceptable start-up method if the timer delay is long enough to avoid setting the current fault latch and the mosfet has adequate safe operating margin. however, for more flexibility in design ( see the design example section), a capacitor from gate to gnd ( figure 1) can be used to limit the v gate slew rate for inrush current control. v gate rises with a slope equal to 10 a/c g (figure 3). the supply inrush current is then limited to: i inrush = c l c g ? 10a once ? v gate exceeds ? v gate (h) , status goes high imped - ance. i cc drops from 300 a to 4 a ( average) during this normal on mode as some circuit blocks are shut down and the internal charge pump periodically turns on when ?v gate droops by 0.7 v or every 15 ms, whichever comes first (figure 7). in the back-to-back mosfet configuration as shown in figure 5, source will also be pulled to gnd via the para- sitic body diode between gate and source, cutting off the load from in. this configuration is suitable in power path control and reverse battery protection applications where in is likely to go below gnd. in the single mosfet configuration ( figure 1), the 1 ma pull-down from gate to gnd also discharges the load capacitor c l to gnd once gate goes below source. overcurrent faultthe 50 mv circuit breaker threshold sets the maximum load current allowed under steady state conditions. however, the ltc4231 allows mild overcurrents during supply or load transients when ? v sense momentarily exceeds 50 mv but stays below the 80 mv analog current limit threshold. for severe overcurrents when ? v sense exceeds 80 mv, the analog current limit amplifier controls ? v gate to regu- late ? v sense to 80 mv. the durations of these transient overcurrents must be less than the circuit breaker delay (t cb ) which can be adjusted using the capacitor c t at the timer pin.when ? v sense exceeds 50 mv, the ltc4231 goes into overcurrent mode. c t is charged with a 50 a pull-up. if the overcurrent is transient and ? v sense goes below 50 mv before timer reaches 1.193 v, the 50 a pull-up on timer switches to a 5 a pull-down. multiple overcurrents with a duty cycle > 10% can thus eventually integrate timer to 1.193 v. when timer reaches 1.193 v, the ltc4231 goes into current fault mode and sets an internal current fault latch. the external mosfet will be cut off by a 1 ma pull-down from gate to gnd while status pull-down is asserted. the time in which ltc4231 stays in overcurrent mode before going into current fault mode is called the circuit breaker delay and is given by: t cb = c t ? 24 [ ms/f] figure 3. inrush control by limiting v gate slew gate 20v/div out 20v/div i load 0.5a/div 20ms/div 4231 f03 start-up normal on debounce turn-off sequence the mosfet switch can be turned off by shdn going low, an ov/uv event, an overcurrent setting the current fault latch or in dropping below its uvlo voltage. under any of these conditions, status pulls low and the mosfet is turned off with a 1 ma current pulling down from gate to gnd. downloaded from: http:///
ltc 4231 12 4321fa for more information www.linear.com/ltc4231 applications information in source gate shdn status voltage fault ?v sense timer gndsw debounce start-up start-up normal on over- current current fault shut- down debounce normal on 4a 4a 4a 4a 300a 300a 300a average i cc 200s 0.3a 4a (i gate(leakage) 0.1a) 4a (i gate(leakage) 0.1a) v ovoff 40ms t cb 40ms 4231 f04 ?v sense(cb) ?v gate(h) 0.7v v timer(h) v timer(l) figure 4. ltc4231-1 overcurrent downloaded from: http:///
ltc 4231 13 4321fa for more information www.linear.com/ltc4231 applications information auto-retry vs latchoff during current fault mode, gate is held low and timer is discharged to gnd. once timer < 0.1 v, average i cc goes to 4 a and the internal current fault latch is ready to be reset. the ltc4231 -2 ( automatic retry) waits for a 500 ms retry delay after which the internal current fault latch is reset and gate ramps up to turn the mosfet back on. the ltc4231 -1 ( latchoff) version does not restart automati - cally. pulling shdn low for >100 s will reset the internal current fault latch. when shdn goes high, gate ramps up after a debounce cycle. alternatively, in can be pulled to gnd for >100 s then cycled back up again. this uvlo event will reset the internal current fault latch and gate ramps up after a debounce cycle. a uv/ov detected at in also resets the internal current fault latch and gate ramps up after a debounce delay.analog current limit loop stability the analog current limit loop on gate is compensated by the parasitic gate capacitance of the external mosfet. no further compensation components are normally required. if a small mosfet with c iss 1 nf is chosen, an r g and c g compensation network connected at gate may be required ( figure 1) to ensure stability. the resistor, r g , connected in series with c g accelerates the mosfet gate recovery after a fast gate pull - down. the value of c g should be 100 nf. an additional 10 resistor ( r5 in figure 1) should be added close to the mosfet gate to prevent possible parasitic oscillation due to trace/wire inductance and capacitance.monitor ov and uv faults when in is above uvlo and shdn is high, an internal clock times a 200 s strobe of the resistive divider at in every 10 ms. during this 200 s strobe, the normally high impedance gndsw is connected to gnd with an internal 80 switch and the comparators connected to uvh, uvl and ov are awakened from sleep mode. the comparators sense the voltages on the resistive divider, and their outputs are latched at the end of the strobe window. if an ov or uv violation is detected, the status pulls low and a 1 ma pull-down will be activated between gate and gnd to turn off the external mosfet. when gate goes <1.2 v, average i cc drops to 4 a as the ltc4231 goes into voltage fault mode. it stays in this mode until a subsequent in strobe sees no ov/uv. the ltc4231 then re-starts after a debounce cycle. strobing the resistive divider reduces power consumption as the external resistors as well as the internal ov/uv comparators do not dissipate power in between strobes. for a 1 m string of resistors used to monitor a v in of 24 v, this strobing scheme reduces the current consumption from 24 a to 0.48 a as the strobing duty cycle is 2% (200s/10ms). the ov/uv comparators dissipate 35 a during in strobing. the 2% duty cycle reduces this to an average current of 0.7 a. note that the response time to an ov/uv event can be as long as 10ms. the four resistors allow three thresholds to be configured. they are the uv rising threshold ( v uvon ), the uv falling threshold ( v uvoff ) and the ov rising threshold ( v ovoff ). the ov falling threshold is set by internal hysteresis to be 1.8% below the ov rising threshold. using the compara - tor threshold as 0.795 v and choosing appropriate values for r total and r4, the resistor values can be calculated as follows: r total = r1 + r2 + r3 + r4 r4 = 0.795v v ovoff ?? ? ?? ? ? r total r3 = v ovoff v uvon ? 1 ?? ? ?? ? ? r4 r2 = v uvon v uvoff ? 1 ?? ? ?? ? ? v ovoff v uvon ?? ? ?? ? ? r4 r1 = u ovoff 0.795v ? 1 ?? ? ?? ? ? r4 ? r3 ? r2 it is recommended that the total value of the resistor string be less than 2 m and traces at uvh, uvl, and ov kept short to minimize parasitic capacitance and improve settling time. downloaded from: http:///
ltc 4231 14 4321fa for more information www.linear.com/ltc4231 applications information reverse input protection negative voltages at in can occur if a battery is plugged in backwards or a negative supply is inadvertently con - nected. back-to-back n-channel mosfets can be used as in figure 5 to prevent the negative voltage from passing to the output load. in, sense, gate and source are protected against reverse inputs of up to C40 v. when the ltc4231's reverse volt - age comparators detect a negative voltage at sense, an internal switch is activated to connect gate to sense. the body diode of m1 pulls source to a diode above sense. since m2 is off and its body diode is in the reverse blocking mode, the negative voltage is blocked by the v ds of m2. figure 6 shows the waveforms when the application circuit in figure 5 is hot plugged to C24 v. due to the parasitic inductance at in, sense and gate, the voltages ring significantly below C24 v. the transzorb helps to clamp the negative undershoot and a 40 v mosfet is selected for m2 to survive this undershoot. figure 5. back-to-back mosfets protect against reverse input figure 6. ltc4231 in reverse input mode sense gate inuvl uvh ov gndsw source status shdn timer ltc4231 m1 si7164dp z1smaj24ca r sense 22.5m m2 si5410du gnd r stat 20k c l 100f uv rising = 23v uv falling = 22v ov rising = 26v v out 24v2a r11020k r x 10? c x 0.1f r21.65k 24v r34.22k r432.4k c t 82nf i load 4231 f05 gate 20v/div out 20v/div in 20v/div 1s/div 4231 f06 downloaded from: http:///
ltc 4231 15 4321fa for more information www.linear.com/ltc4231 applications information achieving low quiescent current table 1 summarizes the average i cc of the various operat- ing modes of the ltc4231. table 1 mode i cc (norm) i cc (max) start-up or overcurrent 300a 600a debounce, normal on, voltage or current fault 4a 10a shutdown 0.3a 1a reverse input C2.5ma C5ma to lower i cc when gate is high, the ltc4231 operates in normal on mode, where the charge pump delivers pulses of current to the gate capacitance ( either an external c g or the parasitic capacitance of the external mosfets) to boost ? v gate to ? v gate(h) followed by sleep periods when the gate capacitance holds up gate. leakage will cause ? v gate to droop during these sleep periods. when the ? v gate low comparator detects ? v gate drooping by more than 0.7 v, it will activate the charge pump to boost ?v gate back to ? v gate(h) before returning to sleep mode. in addition to the ? v gate low comparator, there is a charge pump refresh timer that turns on the charge pump every 15ms to boost ? v gate back to ? v gate(h) . this timer is reset when the charge pump turns on. when in charge pump sleep mode the ltc4231 consumes 2a. when the charge pump is on to deliver a current pulse figure 7. regulating ?v gate during normal on mode figure 8. shdn going low activates shutdown mode ?v gate 2v/div i cc 200a/div 5ms/div 4231 f07 i gate = C0.1a i gate = C1a gate 20v/div source 20v/div status 20v/div shdn 5v/div 20s/div enters shutdown mode 4231 f08 to gate, i cc briefly goes up to 200 a. the amount of leak- age at gate ( i gate(leakage) ) will determine the duty cycle of the charge pump. figure 7 shows start-up and ?v gate regulation ( with different i gate(leakage) ) waveforms from the figure 5 application circuit. as the average current delivered to gate during the cur - rent pulse is around 15 a, the duty cycle of the charge pump for a i gate(leakage) of 0.1 a is 0.1/15 = 0.67%. the average current due to ? v gate regulation is then 0.67% ? 200 a = 1.3 a. when added to the average current due to ov/uv strobing (0.7 a) and charge pump sleep mode current (2 a), the average quiescent current of the ltc4231 during the normal on mode is 1.3a + 0.7a + 2a = 4 a. the normal on mode average supply current can be estimated using the formula: i cc = 2.7a + 13.3 ? i gate(leakage) the typical performance characteristics section shows a graph of average i cc (normal on) against i gate(leakage) . shutdown modewhen shdn goes low, status pulls low and a 1 ma pull-down will be activated between gate and gnd to cut off the external mosfet. when gate reaches <1.2 v, i cc drops to 0.3 a as the ltc4231 goes into shutdown mode. when shdn goes high, gate ramps up after the 40ms debounce cycle. figure 8 shows the application in figure 5 going into shutdown mode. downloaded from: http:///
ltc 4231 16 4321fa for more information www.linear.com/ltc4231 applications information supply transient protection when the capacitances at the input and output are very small, rapid changes in current during an output short- circuit event can cause transients that exceed the 40 v absolute maximum ratings of in, sense and source. to minimize such spikes, use wider traces or heavier trace plating to reduce the power trace inductance. also, bypass locally with a 10 f electrolytic and 0.1 f ceramic if hot plug inrush current is not a concern. alternatively, clamp the input with a transient voltage suppressor ( z1 in figure 5). a 10, 0.1 f snubber damps the response and reduces ringing (r x and c x in figure 5). design example as a design example, take the following specifications for the figure 5 application circuit. the application is rated for a v in of 24 v at 2 a, c l = 100 f. uv rising = 23 v, uv falling = 22v, ov rising = 26v.sense resistor: r sense = ? v sense(cb)(min) 2a = 47mv 2a = 23.5m ? use r sense = 22.5 m for margin. worst case analog current limit: i limit(min) = ? v sense(acl)(min) 22.5m ? = 65mv 22.5m ? = 2.89a i limit(max) = ? v sense(acl)(max) 22.5m ? = 90mv 22.5m ? = 4a calculate the worst case time it takes to charge up c l in analog current limit: t charge(max) = c l ? v in i limit(min) = 100f ? 24v 2.89a = 0.9ms for inrush control using analog current limit, t charge(max) must be less than the circuit breaker delay ( t cb ) for a proper start-up. the worst case power dissipation in mosfet m1 occurs during a severe overcurrent fault when the current is controlled by analog current limit for the duration of t cb : p diss = v in ? i limit(max) = 24v ? 4 a = 96w the soa ( safe operating area) curve for the si7164dp mosfet shows that it can withstand 180 w for 10 ms. so choose a t cb that is less than 10 ms but higher than 0.9 ms (t charge(max) ). in this case, use t cb = 2ms. c t = t cb 24 = 2ms 24 = 0.082f = 82nf if a low inrush current (< ?v sense(cb) ) is preferred, refer to the figure 1 application circuit which uses a gate capaci- tor c g to limit the inrush current. choose i inrush = 0.5a which is set using c g : c g = c l i inrush ? 10a = 1000f 0.5a ? 10a = 20nf the time to charge up c l with 0.5a is: t charge = c l ? v in i inrush = 1000f ? 24v 0.5a = 48ms in this case t charge can be longer than t cb with no start- up issue. the average power dissipation in the mosfet m1 during this start-up is: p diss = v in ? i inrush 2 = 24v ? 0.5a 2 = 6w the soa of the mosfet m1 must be evaluated to ensure that it can withstand 6 w for 48 ms. the soa curve of the si7120adn withstands 10 w for 360 ms, satisfying the requirement. the purpose of mosfet m2 is to block the reverse path from out ( drain of m2) to in when gate pulls to gnd so that in can go lower than out or even negative. choose a 40v mosfet to withstand a worse case reverse dc volt - age of C24 v. the si5410du offers a good choice with a maximum r ds(on) of 18m at v gs = 10v. downloaded from: http:///
ltc 4231 17 4321fa for more information www.linear.com/ltc4231 applications information the in monitoring resistors r1Cr4 should be chosen to yield a total divider resistance of between 1 m to 2 m for both low power and good transient response. using the formulas from the monitor ov and uv faults section, r1Cr4 are calculated as follows ( with all resistor values rounded up to the nearest 1% accurate standard values): choose r1 + r2 + r3 + r4 = 1000k r4 = 0.795v v ovoff ? ? ? ? ? ? ? 1000k ? choose r 4 = 32.4 k to give total divider resistance: r1 + r2 + r3 + r4 = 1060k. r3 = v ovoff v uvon ? 1 ?? ? ?? ? ? r4 = 26v 23v ? 1 ?? ? ?? ? ? 32.4k ? = 4.22k ? r2 = v uvon v uvoff ? 1 ?? ? ?? ? ? v ovoff v uvon ?? ? ?? ? ? r4 = 23v 22v ? 1 ?? ? ?? ? ? 26v 23v ?? ? ?? ? ? 32.4k ? = 1.65k ? r1 = v ovoff 0.795v ? 1 ?? ? ?? ? ? r4 ? r3 ? r2 = 26v 0.795v ? 1 ?? ? ?? ? ? 32.4k ? ? 4.22k ? ? 1.65k ? = 1020k ? layout considerationsto achieve accurate current sensing, a kelvin connection for the sense resistor is recommended. the pcb layout for the resistor should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistors and the power mosfets should include good thermal management techniques for optimal device power dissipation. in hot swap applications where load currents can be high, narrow pcb tracks exhibit more resistance than wider tracks and operate at elevated tem - peratures . 1 oz copper exhibits a sheet resistance of about 0.5m/square. the minimum trace width for 1 oz copper foil is 0.5 mm per amp to make sure the trace stays at a reasonable temperature. using 0.8 mm per amp or wider is recommended. thicker top and bottom copper such as 3oz or more can improve electrical conduction and reduce pcb trace dissipation. if a resistor r 5 ( see figure 1) is used, place it as close as possible to m1's gate input. this will limit the parasitic trace capacitance that leads to m1 self-oscillation. the transient voltage suppressor, z1, when used, should be mounted close to the ltc4231 using short lead lengths. a recommended pcb layout for the sense resistor and back- to back power mosfets is shown in figure 9. ltc4231 mosfet m1 mosfet m2 z1 r sense r stat r5 4231 f09 figure 9. recommended layout downloaded from: http:///
ltc 4231 18 4321fa for more information www.linear.com/ltc4231 applications information sense gate inuvl uvh ov gndsw shdn source status timer ltc4231 ltc2955-1 m1 si7120adn int en kill timer on v in pb z1smaj28ca r sense 45m m2 si5410du out gnd c l 100f uv rising = 25v uv falling = 24v ov rising = 28.5v v out 25v1a r11070k r in 10k c in 100nf r21.47k 25v r34.32k r stat 4.7m r430.9k gnd c t 180nf c2180nf 4231 f10 figure 10. micropower push button and hot swap controllers with reverse battery protection additional applicationsfigure 10 shows a reverse-battery protected application featuring the ltc2955 micropower push - button controller . a press on the push button switch will turn on the ltc4231 while a subsequent press will turn off the ltc4231. in the event the ltc4231 is unable to power-up successfully when en goes high, the status output is fed back to the kill input in order to place the ltc4231 back in the very low-power shutdown mode. figure 11 illustrates a 36 v application with an uv rising threshold of 35 v, an uv falling threshold of 33 v and an ov rising threshold of 38 v. as the in operating voltage is so near to its 40 v absolute maximum rating, a suitable transzorb is not available to protect in. instead, a float - ing gnd architecture is used to help the ltc4231 survive p ossible voltage transients during short circuit events. this architecture is strictly for handling in transients during 36v operation. it does not allow dc v in operation > 39 v. downloaded from: http:///
ltc 4231 19 4321fa for more information www.linear.com/ltc4231 package description ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev a) please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms12) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 C?0.38 (.009 C .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.10 (.201) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) downloaded from: http:///
ltc 4231 20 4321fa for more information www.linear.com/ltc4231 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ud package 12-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1855 rev ?) please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.65 0.05 (4 sides) note:1. drawing conforms to jedec package outline mo-220 variation (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 bottom viewexposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typor 0.25 45 chamfer 11 12 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 C 0.05 (ud12) qfn 0709 rev ? 0.25 0.05 0.50 bsc package outline downloaded from: http:///
ltc 4231 21 4321fa for more information www.linear.com/ltc4231 revision history rev date description page number a 09/15 added h-grade information updated specifications: v gate(l) , i gate(up) , t d(on) , t retry , t period , t sample , t cb 2, 3, 4 3,4 downloaded from: http:///
ltc 4231 22 4321fa for more information www.linear.com/ltc4231 ? linear technology corporation 2014 lt 0915 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4231 related parts typical application part number description comments ltc4361 overvoltage/overcurrent protection controller 220a i q , 2.5v to 5.5v operation, 80v protection ltc4365 ov, uv and reverse supply protection controller 25a i q , 2.5v to 34v operation, C40v reverse input ltc4359 ideal diode controller with reverse input protection 150a i q , 9a in shutdown, 4v to 80v operation ltc4364 surge stopper/hot swap with ideal diode 370a i cc , 4v to 80v operation, C40v reverse input, C20v reverse output ltc2960 nano-current dual voltage monitor 850na i q , 2.5v to 36v operation, 1.5% accuracy ltc4229 ideal diode and hot swap controller 2.9v to 18v operation, 2ma i in , 0.5s ideal diode turn-on/off ltc4232 5a integrated hot swap controller integrated 33m? mosfet with sense resistor, 2.9v to 15v operation ltc2955 pushbutton on/off controller automatic turn-on, 1.2a i q , 1.5v to 36v operation ltc4417 prioritized powerpath? controller 28a i q , 2.5v to 36v operation, C42v reverse input figure 11. 36v hot swap application with reverse protection sense gate inuvl uvh ov gndsw shdn source status timer ltc4231 m1 si7164dp r sense 45m gnd m2 si7120adn out r stat 1m v out 36v1a r1787k r61m r x 10 z2bzx84c39 z3bzx84c39 c x 0.1f r21.1k uv rising = 35v uv falling = 33v ov rising = 38v r31.43k r416.9k c t 270nf 10nf 4231 f11 z1smbj36ca 36v + c l 100f 300 downloaded from: http:///

▲Up To Search▲

Price & Availability of LTC4231HUD-1PBF

	To Download LTC4231HUD-1PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .